1. Field of the Invention
The present invention relates to an emulation device for a single chip microcomputer, and more particularly, to an emulation device for a single chip microcomputer capable of outputting internal status information of a peripheral circuit in a real time manner.
2. Description of Related Art
As an electronic apparatus containing a single chip microcomputer recently becomes more complicated, the amount of software to be executed by the microcomputer increases. On the other hand, the life cycle of such an electronic apparatus is relatively short. As a result, it is important to develop the software in a short time. Therefore, there is a demand for a single chip microcomputer having high level function and performance such that the software can be readily developed using the microcomputer.
In developing software, it is necessary to acquire status information of a peripheral circuit to be controlled by the single chip microcomputer. Specifically, in developing an application program for a real time control system, it is important to collect debugging information such as status information of a peripheral circuit which operates asynchronously with the execution of the program and to display the debugging information on a monitor to show the execution state of the program to a programmer for further increased development efficiency.
FIG. 1 is a diagram of a conventional debugging system generally used to develop the software for the single chip microcomputer. The debugging system is composed of a personal computer 500 and an in-circuit emulator 700 having an in-circuit emulator and connected a target system 600, for emulating the target system 600 while outputting status information. FIG. 2 is a block diagram of the conventional in-circuit emulator 700 for a single chip computer of the microcomputer system. Referring to FIG. 2, the in-circuit emulator 700 is composed of a supervisor CPU 1001 and an emulator chip device 1000. The emulator chip device 1000 emulates the actual operation of a system as a target of emulation. The supervisor CPU 1001 control the whole of emulation operation, monitors signals on an address bus 102 and data bus 103 to control of the emulation chip device 1000, and outputs debug information to the screen of a monitor 1009 via an external bus 1008. Also, the supervisor CPU 1001 sets a supervisor interrupt signal to an active state to temporarily stop the execution of the program by the emulator chip device 1000 and then executes a read instruction to read status data stored in registers in the emulator chip device 1000.
FIG. 3 is a block diagram of the internal structure of the emulator chip device 1000. Referring to FIG. 3, the read operation of status data from peripheral circuits built in the emulator chip device 1000 will be described. As shown in FIG. 3, the emulator chip device 1000 is composed of a central processing unit (CPU) 1020, memory 1010, peripheral circuits 1030 and 1040, and terminals 1022, 1023, 1024, 1025, 1026 and 1027 which are respectively connected to a clock signal 1011, a supervisor interrupt signal 1012, a read signal 1013, a write signal 1014, an address bus 1018 and a data bus 1019. The peripheral circuits 1030 and 1040 are composed of peripheral control circuits 1031 and 1041 for operating as peripheral functions and peripheral status flags 1032 and 1042 for storing the operation results of the peripheral control circuits 1031 and 1041. The peripheral status flags 1032 and 1042 are generally memory mapped. Accordingly, the CPU 1020 can read the state of each flag by use of the address bus 1018, the data bus 1019 and the read signal 1013.
The read signal is outputted from the CPU 1020 to the memory 1010, the peripheral circuits 1030 and 1040, and the external terminal 1025. The write signal 1014 is outputted from the CPU 1020 to the memory 1010, the peripheral circuits 1030 and 1040 and the external terminal 1024. The clock signal 1011 is supplied from the supervisor CPU 1001 to the CPU 1020, the peripheral circuits 1030 and 1040 via the external terminal 1022. The supervisor interrupt signal 1012 is supplied from the supervisor CPU 1001 to the CPU 1020 via the external terminal 1023.
Next, the operation will be described in a case where the program is temporally stopped during the emulation such that the supervisor CPU 1001 can read status data from the peripheral status flag 1042. The supervisor CPU 1001 set the supervisor interrupt signal 1007 to "1", i.e., an active state and transmits it to the emulator chip device 1000 as the supervisor interrupt signal 1012 via the external terminal 1023. The emulator chip device 1000 detects that the supervisor interrupt signal 1012 is "1" and stops the execution of the user program. Then, the supervisor CPU 1001 issues a read command to the emulation chip device 1000 via the data buses 1003 and 1019 via the external terminal 7. The CPU 1020 sets the read signal 1013 to "1" in response to the read command from the supervisor CPU 1001 to read data of the peripheral status flag 1042 by use of the address bus 1018 and the data bus 1019. The CPU 1020 supplies the read data to the supervisor CPU 1001 via the data buses 1019 and 1003 and the external terminal 1027. When receiving the data, the supervisor CPU 1001 outputs the data to a monitor 1009 via the external bus 1008 such that the status data is displayed.
As described above, in the conventional debugging system using a microcomputer system, in order to read the data of the peripheral status flag, the execution of the user program by the CPU 1020 is interrupted in response to the supervisor interrupting signal from the supervisor CPU 1001. For this reason, the data of the peripheral status flag which changes with time cannot be emulated in a real time manner without interrupting the execution of the user program. Alternatively, it could be considered that instructions for reading and outputting the data of the peripheral status flag to the supervisor CPU are incorporated in the user program in advance and the instructions are executed to output the data. In this case, however, the user program needs to be rewritten after debugging and it is complicated.